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?2009 silicon storage technology, inc. s71344-02-000 12/09 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. mpf is a trademark of silicon storage technology, inc. these specifications are subject to change without notice. data sheet features: ? organized as 512k x16 ? single voltage read and write operations ? 1.65-1.95v ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption (typical values at 5 mhz) ? active current: 5 ma (typical) ? standby current: 5 a (typical) ? sector-erase capability ? uniform 2 kword sectors ? block-erase capability ? uniform 32 kword blocks ? fast read access time ? 70 ns ? latched address and data ? fast erase and word-program ? sector-erase time: 36 ms (typical) ? block-erase time: 36 ms (typical) ? chip-erase time: 140 ms (typical) ? word-program time: 28 s (typical) ? automatic write timing ? internal v pp generation ? end-of-write detection ? toggle bit ? data# polling ? cmos i/o compatibility ? jedec standard ? flash eeprom pinouts and command sets ? packages available ? 48-ball tfbga (6mm x 8mm) ? 48-ball wfbga (4mm x 6mm) micro-package ? 48-ball xflga (5mm x 6mm) micro-package ? 48-ball xflga (4mm x 6mm) micro-package ? all non-pb (lead-free) devices are rohs compliant product description the sst39wf800b is a 512k x16 cmos multi-purpose flash (mpf) manufactured with sst proprietary, high-per- formance cmos superflash technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared to alternate approaches. the sst39wf800b writes (program or erase) with a 1.65-1.95v power supply. this device con- forms to jedec standard pin assignments for x16 memo- ries. the sst39wf800b features high-performance word-pro- gramming which provides a typical word-program time of 28 sec. it uses toggle bit or data# polling to detect the completion of the program or erase operation. on-chip hardware and software data protection schemes protects against inadvertent writes. designed, manufactured, and tested for a wide spectrum of applications, the sst39wf800b is offered with a guaranteed typical endur- ance of 100,000 cycles. data retention is rated at greater than 100 years. the sst39wf800b is suited for applications that require convenient and economical updating of program, configu- ration, or data memory. it significantly improves perfor- mance and reliability of all system applications while lowering power consumption. it inherently uses less energy during erase and program than alternative flash technolo- gies. when programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application. for any given voltage range, super- flash technology uses less current to program and has a shorter erase time; therefore, the total energy consumed during any erase or program operation is less than alterna- tive flash technologies. these devices also improve flexibil- ity while lowering the cost for program, data, and configuration storage applications. superflash technology provides fixed erase and program times independent of the number of erase/program cycles that have occurred. consequently, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/pro- gram cycles. to meet surface mount requirements, the sst39wf800b is offered in 48-ball tfbga, 48-ball wfbga, and a 48-ball xflga packages. see figures 2 and 3 for pin assign- ments and table 2 for pin descriptions. 8 mbit (x16) multi-purpose flash sst39wf800b
2 data sheet 8 mbit (x16) multi-purpose flash sst39wf800b ?2009 silicon storage technology, inc. s71344-02-000 12/09 device operation commands, which are used to initiate the memory opera- tion functions of the device, are written to the device using standard microprocessor write sequences. a command is written by asserting we# low while keeping ce# low. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. read the read operation of the sst39wf800b is controlled by ce# and oe#; both have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. see figure 5. word-program operation the sst39wf800b is programmed on a word-by-word basis. the sector where the word exists must be fully erased before programming. programming is accomplished in three steps: 1. load the three-byte sequence for software data protection. 2. load word address and word data. during the word-program operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, whichever occurs first. 3. initiate the internal program operation after the rising edge of the fourth we# or ce#, whichever occurs first. once initiated, the program operation will be completed within 40 s. see figures 6 and 7 for we# and ce# controlled program operation timing diagrams and figure 17 for flowcharts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal program operation, the host is free to perform additional tasks. any commands issued during the internal program operation are ignored. sector-/block-erase operation the sst39wf800b offers both sector-erase and block- erase modes which allow the system to erase the device on a sector-by-sector, or block-by-block, basis. the sector architecture is based on uniform sector size of 2 kword. initiate the sector-erase operation by executing a six-byte command sequence with sector-erase command (30h) and sector address (sa) in the last bus cycle. the block-erase mode is based on uniform block size of 32 kword. initiate the block-erase operation by executing a six-byte command sequence with block-erase command (50h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of-erase operation can be determined using either data# polling or toggle bit methods. see figures 10 and 11 for timing waveforms. any commands issued during the sector- or block-erase operation are ignored. chip-erase operation the sst39wf800b provides a chip-erase operation, which allows the user to erase the entire memory array to the ?1? state. this is useful when the entire device must be quickly erased. initiate the chip-erase operation by executing a six-byte command sequence with chip-erase command (10h) at address 5555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid read is toggl e bit or data# polling. see table 4 for the command sequence, figure 9 for the timing diagram, and figure 20 for the flowchart. any com- mands issued during the chip-erase operation are ignored.
data sheet 8 mbit (x16) multi-purpose flash sst39wf800b 3 ?2009 silicon storage technology, inc. s71344-02-000 12/09 write operation status detection to optimize the system write cycle time, the sst39wf800b provides two software means to detect the completion of a program or erase write cycle. the software detection includes two status bits?data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase operation. the completion of the nonvolatile write is asynchronous with the system; therefore, either a data# polling or toggle bit read may occur simultaneously with the completion of the write cycle. if this occurs, the system may get an erro- neous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . to prevent spurious rejection in the event of an erroneous result, the software routine must include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. data# polling (dq 7 ) when the sst39wf800b is in the internal program oper- ation, any attempt to read dq 7 will produce the comple- ment of the true data. once the program operation is complete, dq 7 will produce true data. although dq 7 may have valid data immediately following the completion of an internal write operation, the remain- ing data outputs may still be invalid. valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s . during an internal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal eras e operation is complete, dq 7 will produce a ?1?. the data# polling is valid afte r the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block-, or chip-erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 8 for data# polling timing diagram and figure 18 for a flowchart. toggle bit (dq 6 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating ?1?s and ?0?s, i.e., toggling between ?1? and ?0?. when the program or erase operation is complete, the dq 6 bit will stop toggling and the device is ready for the next operation. the toggle bit is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block- or chip-erase, the toggle bit is valid after the rising edge of sixth we# (or ce#) pulse. see figure 0-1 for toggle bit timing diagram and figure 18 for a flowchart. data protection the sst39wf800b provides both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection : a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection : the write operation is inhibited when v dd is less than 1.0v. write inhibit mode : forcing oe# low, ce# high, or we# high will inhibit the write oper ation. this prevents inadvert- ent writes during power-up or power-down. software data protection (sdp) the sst39wf800b provides the jedec approved soft- ware data protection scheme for all data alteration opera- tions, i.e., program and erase. any program operation requires the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte sequence. this group of devices are shipped with the software data protection permanently enabled. see table 4 for the specific software command codes. during sdp command sequence, invali d commands will abort the device to read mode within t rc . the contents of dq 15 - dq 8 can be v il or v ih , but no other value, during any sdp command sequence. common flash memory interface (cfi) the sst39wf800a contains the cfi information that describes the characteristics of the device, and supports both the original sst cfi query mode implementation for compatibility with existing sst devices, as well as the gen- eral cfi query mode. to enter the sst cfi query mode, the system must write the three-byte sequence, same as the product id entry command, with 98h (cfi query command) to address 5555h in the last byte sequence.
4 data sheet 8 mbit (x16) multi-purpose flash sst39wf800b ?2009 silicon storage technology, inc. s71344-02-000 12/09 to enter the general cfi query mode, the system must write a one-byte sequence using the entry command with 98h to address 55h. once the device enters the cfi query mode, the system can read cfi data at the addresses given in tables 5 through 7. the system must write the cfi exit command to return to read mode from the cfi query mode. product identification the product identification mode identifies the device as the sst39wf800b and manufacturer as sst. this mode is accessed by software operations. use software product identification operation to identify the part (i.e., using the device id) when using multiple manufacturers in the same socket. for details, see table 4 for software operation, figure 12 for the software id entry and read timing diagram, and figure 19 for the software id entry command sequence flowchart. product identification mode exit/ cfi mode exit to return to the standard read mode, exit the software product identification mode. issue the software id exit command sequence which returns the device to the read mode. the software id exit command may also be used to reset the device to the read mode after any inadvertent transient condition that causes the device to behave abnormally, e.g., not read correctly. the software id exit/cfi exit command is ignored during an internal program or erase operation. see table 4 for software command codes, figure 14 for timing waveform, and figure 19 for a flowchart. table 1: product identification table address data manufacturer?s id 0000h 00bfh device id sst39wf800b 0001h 273eh t1.0 1344
data sheet 8 mbit (x16) multi-purpose flash sst39wf800b 5 ?2009 silicon storage technology, inc. s71344-02-000 12/09 figure 1: functional block diagram figure 2: pin assignments for 48-ball wfbga and 48-ball xflga y-decoder i/o buffers and data latches 1344 b1.0 address buffer & latches x-decoder dq 15 - dq 0 memory address oe# ce# we# superflash memory control logic a2 a1 a0 ce# v ss a4 a3 a5 dq8 oe# dq0 a6 a7 a18 dq10 dq9 dq1 a17 nc nc dq2 nc dq3 nc v dd we# dq12 nc nc nc dq13 a9 a10 a8 dq4 dq5 dq14 a11 a13 a12 dq11 dq6 dq15 a14 a15 a16 dq7 v ss top view (balls facing down) a b c d e f g h j k l 6 5 4 3 2 1 1344 48-wfbga m2q p02.0 sst39wf800b
6 data sheet 8 mbit (x16) multi-purpose flash sst39wf800b ?2009 silicon storage technology, inc. s71344-02-000 12/09 figure 3: pin assignments for 48-ball tfbga table 2: pin description symbol pin name functions a ms 1 -a 0 1. a ms = most significant address a ms = a 18 for sst39wf800b address inputs to provide memory addresses. during sector-erase a ms -a 11 address lines will select the sector. during block-erase a ms -a 15 address lines will select the block. dq 15 -dq 0 data input/output to ou tput data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply to provide power supply voltage: 1.65-1.95v for sst39wf800b v ss ground nc no connection unconnected pins. t2.0 1344 table 3: operation modes selection mode ce# oe# we# dq address read v il v il v ih d out a in program v il v ih v il d in a in erase v il v ih v il x 1 1. x can be v il or v ih , but no other value. sector or block address, xxh for chip-erase standby v ih x x high z x write inhibit x v il x high z/ d out x xxv ih high z/ d out x product identification software mode v il v il v ih see table 4 t3.0 1344 1344 48-tfbga p01.0 sst39wf800b top view (balls facing down) 6 5 4 3 2 1 a b c d e f g h a13 a9 we# nc a7 a3 a12 a8 nc nc a17 a4 a14 a10 nc a18 a6 a2 a15 a11 nc nc a5 a1 a16 dq7 dq5 dq2 dq0 a0 nc dq14 dq12 dq10 dq8 ce# dq15 dq13 v dd dq11 dq9 oe# v ss dq6 dq4 dq3 dq1 v ss
data sheet 8 mbit (x16) multi-purpose flash sst39wf800b 7 ?2009 silicon storage technology, inc. s71344-02-000 12/09 table 4: software command sequence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 word-program 5555h aah 2aaah 55h 5555h a0h wa 3 data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 4 30h block-erase 5555h aah 2aaah 55 h 5555h 80h 5555h aah 2aaah 55h ba x 4 50h chip-erase 5555h aah 2aaah 55h 555 5h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 5,6 5555h aah 2aaah 55h 5555h 90h sst cfi query entry 5 5555h aah 2aaah 55h 5555h 98h general cfi query mode 55h 98h software id exit 7 / cfi exit xxh f0h software id exit 7 / cfi exit 5555h aah 2aaah 55h 5555h f0h t4.0 1344 1. address format a 14 -a 0 (hex), addresses a ms- a 15 can be v il or v ih , but no other value, for the command sequence. a ms = most significant address a ms = a 18 for sst39wf800b 2. dq 15 -dq 8 can be v il or v ih , but no other value, for the command sequence 3. wa = program word address 4. sa x for sector-erase; uses a ms -a 11 address lines ba x for block-erase; uses a ms -a 15 address lines 5. the device does not remain in software product id mode if powered down. 6. with a ms -a 1 = 0; sst manufacturer?s id = 00bfh, is read with a 0 = 0, sst39wf800b device id = 273eh, is read with a 0 = 1. 7. both software id exit operations are equivalent table 5: cfi query identification string 1 for sst39wf800b 1. refer to cfi publication 100 for more details. address data data 10h 0051h query unique ascii string ?qry? 11h 0052h 12h 0059h 13h 0001h primary oem command set 14h 0007h 15h 0000h address for primary extended table 16h 0000h 17h 0000h alternate oem command set (00h = none exists) 18h 0000h 19h 0000h address for alternate oem extended table (00h = none exits) 1ah 0000h t5.0 1344
8 data sheet 8 mbit (x16) multi-purpose flash sst39wf800b ?2009 silicon storage technology, inc. s71344-02-000 12/09 table 6: system interface information for sst39wf800b address data data 1bh 0016h v dd min (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 0020h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 0000h v pp min (00h = no v pp pin) 1eh 0000h v pp max (00h = no v pp pin) 1fh 0005h typical time out for word-program 2 n s (2 5 = 32 s) 20h 0000h typical time out for min size buffer program 2 n s (00h = not supported) 21h 0005h typical time out for individual sector/block-erase 2 n ms (2 5 = 32 ms) 22h 0007h typical time out for chip-erase 2 n ms (2 7 = 128 ms) 23h 0001h maximum time out for word-program 2 n times typical (2 1 x 2 5 = 64 s) 24h 0000h maximum time out for buffer program 2 n times typical 25h 0001h maximum time out for individual sector/block-erase 2 n times typical (2 1 x 2 5 = 64 ms) 26h 0001h maximum time out for chip-erase 2 n times typical (2 1 x 2 7 = 256 ms) t6.0 1344 table 7: device geometry information for sst39wf800b address data data 27h 0014h device size = 2 n byte (14h = 20; 2 20 = 1 mbyte) 28h 0001h flash device interface description; 0001h = x16-only asynchronous interface 29h 0000h 2ah 0000h maximum number of byte in multi-byte write = 2 n (00h = not supported) 2bh 0000h 2ch 0002h number of erase sector/block sizes supported by device 2dh 00ffh sector information (y + 1 = numb er of sectors; z x 256b = sector size) 2eh 0000h y = 255 + 1 = 256 sectors (00ffh = 255) 2fh 0010h 30h 0000h z = 16 x 256 bytes = 4 kbyte/sector (0010h = 16) 31h 000fh block information (y + 1 = number of blocks; z x 256b = block size) 32h 0000h y = 15 + 1 = 16 blocks (000fh = 15) 33h 0000h 34h 0001h z = 256 x 256 bytes = 64 kbyte/block (0100h = 256) t7.0 1344
data sheet 8 mbit (x16) multi-purpose flash sst39wf800b 9 ?2009 silicon storage technology, inc. s71344-02-000 12/09 electrical specifications absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v voltage on a 9 pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to 11v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds 1. excluding certain with-pb 32-plcc units, all packages are 260 c capable in both non-pb and with-pb solder versions. certain with-pb 32-plcc package types are capable of 240 c for 10 seconds; please consult the factory for the latest information. output short circuit current 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 2. outputs shorted for no more than one second. no more than one output shorted at a time. operating range range ambient temp v dd commercial 0c to +70c 1.65-1.95v industrial -40c to +85c 1.65-1.95v ac conditions of test input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 15 and 16
10 data sheet 8 mbit (x16) multi-purpose flash sst39wf800b ?2009 silicon storage technology, inc. s71344-02-000 12/09 power-up specifications all functionalities and dc specif ications are specified for a v dd ramp rate faster than 1v per 100 ms (0v to 1.8v in less than 180 ms). in addition, a v dd ramp rate slower than 1v per 20 s is recommended. see table 8 and figure 4 for more information. figure 4: power-up reset diagram table 8: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. v dd min to read operation 100 s t pu-write 1 v dd min to write operation 100 s t8.0 1344 1344 f37.1 v dd ce# t pu-read v dd min 0v
data sheet 8 mbit (x16) multi-purpose flash sst39wf800b 11 ?2009 silicon storage technology, inc. s71344-02-000 12/09 dc characteristics table 9: dc operating characteristics, v dd = 1.65-1.95v 1 1. typical conditions for the active current shown on t he front page of the data sheet are average values at 25c (room temperature), and v dd = 1.8v. not 100% tested. symbol parameter limits test conditions min max units i dd power supply current address input=v ilt /v iht, at f=5 mhz, v dd =v dd max read 15 ma ce#=v il , oe#=we#=v ih , all i/os open program and erase 20 ma ce#=we#=v il , oe#=v ih i sb standby v dd current 2 2. 40 a is the maximum i sb for all sst39wf800b commercial grade devices. 40 a is the maximum i sb for all 39wf800a industrial grade devices. for all sst39wf800b commercial and industrial devices, i sb typical is under 5 a. 40 a ce#=v dd , v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.2v dd v dd =v dd min v ih input high voltage 0.8v dd vv dd =v dd max v ol output low voltage 0.1 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.1 v i oh =-100 a, v dd =v dd min t9.0 1344 table 10: capacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t10.0 1344 table 11: reliability characteristics symbol parameter minimum specification units test method n end 1,2 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. 2. n end endurance rating is qualified as a 10,000 cycl e minimum for the whole device. a sector- or block-level rating would result in a higher minimum specification. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t11.0 1344
12 data sheet 8 mbit (x16) multi-purpose flash sst39wf800b ?2009 silicon storage technology, inc. s71344-02-000 12/09 ac characteristics table 12: read cycle timing parameters symbol parameter 70 ns units min max t rc read cycle time 70 ns t ce chip enable access time 70 ns t aa address access time 70 ns t oe output enable access time 35 ns t clz 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. ce# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 ce# high to high-z output 40 ns t ohz 1 oe# high to high-z output 40 ns t oh 1 output hold from address change 0 ns t12.0 1344 table 13: program/erase cycle timing parameters symbol parameter min max units t bp word-program time 40 s t as address setup time 0 ns t ah address hold time 50 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 50 ns t wp we# pulse width 50 ns t wph 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. we# pulse width high 30 ns t cph 1 ce# pulse width high 30 ns t ds data setup time 50 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 50 ms t be block-erase 50 ms t sce chip-erase 200 ms t13.0 1344
data sheet 8 mbit (x16) multi-purpose flash sst39wf800b 13 ?2009 silicon storage technology, inc. s71344-02-000 12/09 figure 5: read cycle timing diagram figure 6: we# controlled program cycle timing diagram 1344 f03.0 address a ms-0 dq 15-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz note: a ms = most significant address a ms = a 18 for sst39wf800b 1344 f04.0 address a ms-0 dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs ce# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# we# t bp note: a ms = most significant address a ms = a 18 for sst39wf800b x can be v il or v ih, but no other value.
14 data sheet 8 mbit (x16) multi-purpose flash sst39wf800b ?2009 silicon storage technology, inc. s71344-02-000 12/09 figure 7: ce# controlled prog ram cycle timing diagram figure 8: data# polling timing diagram 1344 f05.0 address a ms-0 dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# ce# t bp note: a ms = most significant address a ms = a 18 for sst39wf800b x can be v il or v ih, but no other value. 1344 f06.0 address a ms-0 dq 7 data data# data# data we# oe# ce# t oeh t oe t ce t oes note: a ms = most significant address a ms = a 18 for sst39wf800b
data sheet 8 mbit (x16) multi-purpose flash sst39wf800b 15 ?2009 silicon storage technology, inc. s71344-02-000 12/09 figure 0-1: toggle bit timing diagram figure 9: we# controlled chip-erase timing diagram 1344 f07.0 address a ms-0 dq 6 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs note: a ms = most significant address a ms = a 18 for sst39wf800b 1344 f08.0 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx10 xx55 xxaa xx80 xxaa 5555 oe# ce# six-byte code for chip-erase t sce t wp note: this device also supports ce # controlled chip-erase operation the we# and ce# signals are interchange- able as long as minimum ti mings are met. (see table 13) a ms = most significant address a ms = a 18 for sst39wf800b x can be v il or v ih, but no other value.
16 data sheet 8 mbit (x16) multi-purpose flash sst39wf800b ?2009 silicon storage technology, inc. s71344-02-000 12/09 figure 10: we# controlled block-erase timing diagram figure 11: we# controlled sector-erase timing diagram 1344 f09.0 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx50 xx55 xxaa xx80 xxaa ba x oe# ce# six-byte code for block-erase t be t wp note: this device also supports ce# controlled bl ock-erase operation the we# and ce# signals are interchangeable as long as minimu m timings are met. (see table 13) a ms = most significant address a ms = a 18 for sst39wf800b x can be v il or v ih, but no other value. 1344 f10.0 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx30 xx55 xxaa xx80 xxaa sa x oe# ce# six-byte code for sector-erase t se t wp note: this device also supports ce# controlled se ctor-erase operation the we# and ce# signals are interchangeable as long as minimu m timings are met. (see table 13) a ms = most significant address a ms = a 18 for sst39wf800b x can be v il or v ih, but no other value.
data sheet 8 mbit (x16) multi-purpose flash sst39wf800b 17 ?2009 silicon storage technology, inc. s71344-02-000 12/09 figure 12: software id entry and read figure 13: sst cfi query entry and read 1344 f11.0 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 note: device id = 273fh for sst39wf800b x can be v il or v ih, but no other value. 1344 f12.0 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 oe# ce# three-byte sequence for sst cfi query entry t wp t wph t aa xx55 xxaa xx98 note: x can be v il or v ih, but no other value.
18 data sheet 8 mbit (x16) multi-purpose flash sst39wf800b ?2009 silicon storage technology, inc. s71344-02-000 12/09 figure 14: software id exit/cfi exit figure 15: ac input/output reference waveforms figure 16: a test load example 1344 f13.0 address a 14-0 dq 15-0 t ida t wp t whp we# sw0 sw1 sw2 5555 2aaa 5555 three-byte sequence for software id exit and reset oe# ce# xxaa xx55 xxf0 note: x can be v il or v ih, but no other value. 1344 f14.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (v dd ) for a logic ?1? and v ilt (v ss ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times are (10% ? 90%) <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1344 f15.0 to tester to dut c l v dd 25k 25k
data sheet 8 mbit (x16) multi-purpose flash sst39wf800b 19 ?2009 silicon storage technology, inc. s71344-02-000 12/09 figure 17: word-program algorithm 1344 f16.0 start load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xxa0h address: 5555h load word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed note: x can be v il or v ih , but no other value.
20 data sheet 8 mbit (x16) multi-purpose flash sst39wf800b ?2009 silicon storage technology, inc. s71344-02-000 12/09 figure 18: wait options 1344 f17.0 wait t bp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
data sheet 8 mbit (x16) multi-purpose flash sst39wf800b 21 ?2009 silicon storage technology, inc. s71344-02-000 12/09 figure 19: software id/cfi command flowcharts 1344 f18.0 load data: xxaah address: 5555h software id entry command sequence load data: xx55h address: 2aaah load data: xx90h address: 5555h wait t ida read software id load data: xxaah address: 5555h cfi query entry command sequence load data: xx55h address: 2aaah load data: xx98h address: 5555h wait t ida read cfi data load data: xxaah address: 5555h software id exit/cfi exit command sequence load data: xx55h address: 2aaah load data: xxf0h address: 5555h load data: xxf0h address: xxh return to normal operation wait t ida wait t ida return to normal operation note: x can be v il or v ih , but no other value.
22 data sheet 8 mbit (x16) multi-purpose flash sst39wf800b ?2009 silicon storage technology, inc. s71344-02-000 12/09 figure 20: erase command sequence 1344 f19.0 load data: xxaah address: 5555h chip-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx10h address: 5555h load data: xxaah address: 5555h wait t sce chip erased to ffffh load data: xxaah address: 5555h sector-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx30h address: sa x load data: xxaah address: 5555h wait t se sector erased to ffffh load data: xxaah address: 5555h block-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx50h address: ba x load data: xxaah address: 5555h wait t be block erased to ffffh note: x can be v il or v ih , but no other value.
data sheet 8 mbit (x16) multi-purpose flash sst39wf800b 23 ?2009 silicon storage technology, inc. s71344-02-000 12/09 product ordering information valid combinations for sst39wf800b sst39wf800b-70-4c-b3ke sst39wf800b-70-4i-b3ke SST39WF800B-70-4C-C2QE sst39wf800b-70-4i-c2qe sst39wf800b-70-4c-maqe sst39wf800b-70-4i-maqe sst39wf800b-70-4c-caqe sst39wf800b-70-4i-caqe note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. environmental attribute e 1 = non-pb package modifier k = 48 balls q = 48 balls (66 possible positions) package type b3 = tfbga (0.8mm pitch, 6mm x 8mm) c2 = xflga (0.5mm pitch, 5mm x 6mm) ma= wfbga (0.5mm pitch, 4mm x 6mm) ca = xflga (0.5mm pitch, 4mm x 6mm) temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles read access speed 70 = 70 ns device density 800 = 8 mbit voltage w = 1.65-1.95v product series 39 = multi-purpose flash 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?. sst 39 wf 800b - 70 - 4c - b3k e xx x x xxx x-xx -x x -xx x x
24 data sheet 8 mbit (x16) multi-purpose flash sst39wf800b ?2009 silicon storage technology, inc. s71344-02-000 12/09 packaging diagrams figure 21: 48-ball thin-profile, fine-pitch ball grid array (tfbga) 6mm x 8mm sst package code: b3k figure 22: 48-ball extremely thin-profile, fine-pitch land grid array (xflga) 5mm x 6mm sst package code: c2q a1 corner h g f e d c b a a b c d e f g h bottom view top view side view 6 5 4 3 2 1 6 5 4 3 2 1 seating plane 0.35 0.05 1.10 0.10 0.12 6.00 0.20 0.45 0.05 (48x) a1 corner 8.00 0.20 0.80 4.00 0.80 5.60 48-tfbga-b3k-6x8-450mic-4 note: 1. complies with jedec publication 95, mo-210, variant 'ab-1', although some dimensions may be more stringent. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm) 1mm l k j h g f e d c b a abcdefghjkl 6 5 4 3 2 1 6 5 4 3 2 1 0.50 0.50 bottom view 5.00 0.08 0.29 0.05 (48x) a1 indicator 4 6.00 0.08 2.50 5.00 a1 corner top view 48-xflga-c2q-5x6-29mic-nr note: 1. although many dimensions are similar to those of jedec publication 95, mo-222, this specific package is not registered. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.08 mm 4. no bump is present in position a1; a gold-colored indicator is present. 1mm detail side view seating plane 0.04 + 0.025/ - 0.015 0.52 max. 0.473 nom. 0.08
data sheet 8 mbit (x16) multi-purpose flash sst39wf800b 25 ?2009 silicon storage technology, inc. s71344-02-000 12/09 figure 23: 48-ball very-very-thin-profile, fine-pitch ball grid array (wfbga) 4mm x 6mm sst package code: maq figure 24: 48-ball extremely thin-profile, fine-pitch land grid array (xflga) 4mm x 6mm sst package code: caq l k j h g f e d c b a abcdefghjkl 6 5 4 3 2 1 6 5 4 3 2 1 0.50 0.50 bottom view 4.00 0.08 0.32 0.05 (48x) 6.00 0.08 2.50 5.00 a1 corner top view 48-wfbga-maq-4x6-32mic-2.0 note: 1. complies with jedec publication 95, mo-207, variant cb-4 except nominal ball size is larger and bottom side a1 indicator is triangle at corner. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.08 mm 4. ball opening size is 0.29 mm ( 0.05 mm) 1mm detail side view seating plane 0.20 0.06 0.73 max. 0.636 nom. 0.08 a1 indicator l k j h g f e d c b a abcdefghjkl 6 5 4 3 2 1 6 5 4 3 2 1 0.50 0.50 bottom view 4.00 0.08 0.29 0.05 (48x) 6.00 0.08 2.50 5.00 a1 corner top view 48-xflga-caq-4x6-29mic-6.0 note: 1. complies with jedec publication 95, mo-207, variant czb-4, dimensions except the bump height is much less, and the a1 indicator is different. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.08 mm. 4. for low-profile mounting on pcb, sst recommends underfill for best solder joint reliability. 1mm detail side view seating plane 0.04 +0.025/-0.015 0.52 max. 0.473 nom. 0.08 a1 indicator
26 data sheet 8 mbit (x16) multi-purpose flash sst39wf800b ?2009 silicon storage technology, inc. s71344-02-000 12/09 table 14: revision history number description date 00 ? initial release of data sheet feb 2007 01 ? added ?power-up specifications? on page 10 ? removed the m2qe and mbqe packages ? added y1qe package information jul 2007 02 ? eol of all y1qe parts. replacement parts are maqe parts listed in this document. ? added information for the maqe and caqe packages. dec 2009 silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

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